1. Field of the Invention
The present invention relates to a semiconductor device, in particularly, to a layout of the semiconductor device which make it possible that electric characteristics of two transistors with the same structures as each other: so-called pair transistors, are manufactured with good manufacturing yield.
2. Description of the Related Art
A semiconductor device is manufactured by transferring a mask pattern in which a circuit configuration is laid out on a substrate to form a pattern of the configuration thereon. However, even if a mask pattern is prepared so as to satisfy circuit characteristics, an actual device manufactured on the substrate by using the pattern results in one without electric characteristics as expected when a dimensional difference due to parameter-related fluctuations in a manufacturing process arises. For example, even if masks with gate channel lengths L and gate channel widths W same as design values are prepared, actual devices formed with difference parameters from mask data when fluctuations of a manufacturing process or misalignment of masks for forming contacts are occurred.
Especially, in a case of a sense amplifier section or the like where a small current is employed, current amounts in halves of the circuit that are configured in symmetry with each other come into a state of off balance due to dimensional difference in actual layout, entails deterioration of electric characteristics and causes of defects.
Transistors (N1 and N2 of an A section of FIG. 8) that have symmetrical configurations with each other and which are required to have equal capabilities to each other have conventionally been manufactured with a drain region commonly used by two transistors as shown in FIG. 6, or alternatively with a source region commonly used by two transistors as shown in FIG. 7. Accordingly there has been arisen a problem that in a process step to manufacture such pair transistors, electric characteristics of the pair transistors become different from each other due to a dimensional difference caused by fluctuation of a manufacturing process.
This is a cause of a malfunction of a circuit, when the circuit has a symmetrical configuration as shown in FIG. 8 and halves of the circuit both operate under a difference of currents therebetween.
Further an actual width of a gate channel finally results in the sum of a mask design value (W)+a move-in of an insulating layer xcex94W, relative to a mask design value. The move-in of the insulating layer xcex94W causes in manufacture in which the insulating layer forming on a diffused region invades the diffused region in thermal diffusion. In an actual design of a mask, dimensions of a mask pattern are determined in consideration of a move-in of an insulating layer xcex94W in order to achieve high design precision. However the move-in xcex94W arises in thermal diffusion is influenced by unexpected fluctuations of parameters in manufacture. Therefore it is difficult to avoid dimensional dispersion occurring beyond a design value xcex94W from occurring.
As a difference of an actual width dispersion from a design tolerance xcex94W is larger, a value of a channel width expected in proportion to the number of branch gates obtained division is not realized, and the number of branch gates or width of each branch gate is affected corresponding to a product of a move-in of an insulating layer xcex94W * the number of branch gates. Therefore, if pair transistors in axial symmetry with each other are different in the number of branch gates from each other, it causes difference in actual channel width between the transistors completed, leading to a difference in performance therebetween as well.
Further, there arises a difference in actual gate width between an inner portion and an outer portion in a chip due to a difference in pattern packing density between an array section with a periodic pattern in which repeated gate patterns are densely packed in same intervals and a peripheral section with single patterns sparsely distributed as compared with the array section.
An additional difference in actual gate width between a densely packed section and a sparsely distributed section in the same device occurs according to a degree of light straying-in under a pattern or a condition of light reflection in exposure.
While, in Japanese Patent Laid-Open No. 5-206245 and Japanese Patent Laid-Open No. 3-116726, dummy gates are employed in order to eliminate dimensional dispersion caused by a difference in pattern packing density according to regions where gates are arranged, the published documents have disclosed a technique on a circuit configured of single transistors, but not a technique on a circuit including pair transistors. Further, in Japanese Patent Laid-Open No. 62-173810, there has only been disclosed a transistor with a gate divided into a plurality of branch gates.
Accordingly, it is an object of the invention to provide a semiconductor device having transistors with same electric characteristics.
It is another object of the present invention to provide a semiconductor device which can be manufactured while a dimensional dispersion in actual gate width according to light straying-in or light reflection in exposure is prevented from occurring and which makes it possible that transistors with same electric characteristics, such as pair transistors, are produced to high precision with good manufacturing yield.
It is another object of the present invention to provide pair transistors well suited for constructing a sense amplifier section employing a small current.
These and other objects of the present invention will be apparent to those of skill in the art from the appended claims when in light of the following specification and accompanying figures.
A semiconductor device according to the present invention includes a first transistor having a first gate put between a first source and a first drain; a second transistor arranged adjacent to the first transistor, the second transistor having a second gate put between a second source and a second drain, the second gate arranged parallel to the first gate; a first dummy gate arranged between the first drain and the second source and parallel to the first gate; a second dummy gate arranged adjacent to the first source and parallel to the first gate; and a third dummy gate arranged adjacent to the second drain and parallel to the first gate.